Recent commercial availability of large MOS memory chips has made possible substantial reduction in the price per bit of electronic memory devices. Also the rising costs of software development and the decreasing ratio of hardware cost to software cost, combined with new, lower-cost memory is creating a demand for larger memories in contemporary computer equipment. The ability to expand the memory capability of certain known computing equipment is severely limited, however, because inexpensive and efficient means of increasing the memory address space were not available during the design states of earlier equipment. Also, different memory technologies usually cannot be combined in a given computer. In addition, because multiple processors are unable to share a common memory and multiple-port, independent memory access is not possible. These disadvantages are overcome in accordance with the present invention by utilizing improved bank switching, multiple dedicated memory controllers, and independent multiple access ports for arrays of memory modules.
One known technique for extending the memory addressing range of a computer is bank switching, as illustrated in FIG. 1. One typical embodiment uses a many position switch in the memory control device 9 which activates one of the possible n modules 12-15 of memory at any one time. The processor 17 of the computer system can execute an instruction that selects one out of the n available modules to be active at any one time. This module will remain active until another bank switch instruction is executed, enabling another module of memory, and will react to all addresses of information and commands supplied to the processor 17. In FIG. 1 the switch is shown in position 1 which activates module 13 and no other module of memory. This prior art technique of extending memory has the disadvantage that all of the memory available to the processor 17 at any one time is switched out and replaced when a bank switch instruction occurs. This necessitates duplicating information which is desirable always to have present in memory in each of the banks and necessitates having a table present in each memory to designate where certain other information is stored. This wastes considerable memory space with concomitant increases in the cost of the system. It also necessitates executing many bank switch instructions, for example, to get to information shared by many programs throughout the memory with concomitant increases in execution times in those routines. Also, prior art memory techniques can only be expanded by adding more modules which are accessible only by bank switch instruction execution.
In contrast, the present invention overcomes these problems by allowing any portion of memory (up to all of the memory) to be always present in the memory address space of a processor (or other memory-using devices commonly known as Random Access Channels (RAC), Direct Memory Access Channels (DMA), Intelligent Device Controllers (IDC), or the like) whether a bank switch occurs or not. The memory of the present invention is configurable in steps so that in the address space any quantum (where a quantum is the smallest switchable unit) of memory may remain present while any other quantum is switched in or out of the address space, thus allowing many switchable portions of memory within the address space of memory-using devices. This feature of the invention greatly enhances the flexibility of managing the memory resources of an operating system. Since any quantum of memory may remain present permanently or temporarily in the address space of the using devices information, programs or subprograms shared by various other programs may always be present within the address space of the using devices and thus do not have to be duplicated in each section of memory in order to be immediately available to those programs or processors. In addition, the present invention makes it possible to expand memory by either adding more quanta of memory within the address space of the using device or devices or by increasing the number of quanta which may take the place (by bank switching) of the quanta within the address space.
A conventional technique of sharing memory resource between several memory-using devices is illustrated in FIG. 2. This technique makes it possible for several devices to access a common memory and allows these devices to communicate with each other. However, since there is only one port to the memory an extremely fast memory is required to service all of the using devices (i.e. the throughput of the memory must be n times the throughput of a single using device, (where all using devices are assumed to have the same throughputs) in order to be on a parity with the service supplied where each device has its own separate memory. It is usually not possible to have such a memory subsystem in conventional computer systems due to the tremendous operating speeds required. This usually necessitates either offering less capability than might otherwise be possible if each device had its own memory and the means for communicating therebetween, or of avoiding some operating objectives because sufficient throughput is not available or the memory cost would be prohibitively high.
These disadvantages are overcome in accordance with the present invention which provides the means for sharing memory between two or more memory-using devices. One device using the memory does not interfere with, or reduce the throughput available to, another memory-using device. This is accomplished in accordance with the present invention by allowing other devices (or sets of devices) to use the quanta of memory which are switched out of the address space of one memory-using device. Thus, N quanta of memory may be shared by two memory-using devices such as two central processors and, while one quantum is switched into the memory space of one such processor, the other processor may use one of the other N-1 quanta of memory not used by the one processor. This means that N quanta of memory may be shared between from two to N memory-using devices with each device having essentially its own separate memory and, therefore, sufficient throughput to accomplish its task without interfering with any of the other N number of memory-using devices. The present invention also resolves the problem that occurs when two or more memory-using devices try to access the same quantum of memory at the same time. In addition, the present invention is operable with the memory-using devices of many known computing systems and thus may be used in, or as replacements for, the memory in systems for which the software has already been written.
Certain known contemporary computing systems allow mixing of a few types of memory technologies within a single system, subject, however, to many restraints upon the types of memories which may be mixed. This mixing of different memory technologies within a single memory system is desirable in that the cost/performance ratios of the system can be optimized and selected memory technologies may be included in the memory system because of certain desirable features (PROMS, ROMS, processing memories, etc.) which they possess. Also, as memory technology advances, it is desirable to be able to incorporate such new technologies into compatible memory systems to upgrade and enhance their performance specifications.
The present invention allows many different types of memory to be mixed within a single system by the inclusion of a separate control-data bus which handles all data and control signals between memory controller and its array of memory units. This allows the memory controller to be an interface element between the memory technology and the technology of the memory-using device or devices. Thus, a controller may be constructed within the framework of the present invention for each of the many types of memory technologies available and allow mixing of these many types of memory technologies. Also, appropriate means are provided to accomodate refreshing and non-refreshing types of memory technologies, DRO (Destructive Read Out) and NDRO (Non-Destructive Read Out), random, sequential, and serial read/write or read-only types of memories, and memories which require different power supplies in operation. This is accomplished in accordance with the present invention using different controllers for different types of memory technology involved within a single memory system.